An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

This paper presents three CMOS power amplifiers (PA) which realize wide-tunable output impedance matching. For realization of multi-standard and single-chip transceiver, the prototypes were fabricated by 0.18 µm CMOS process. The proposed PAs can achieve a tunable impedance matching within a wide frequency range by utilizing a resistive feedback and parallel resonator with an inductor and capacitor array. Therefore, the proposed PA has a realization possibility of isolator-less PA which contributes to decrease die area including external component. In other words, the PAs have tunable impedance matching function at their output ends. With a 3.3-V supply, three power amplifiers can cover frequency ranges of 0.9–3.0 GHz, 2.1–5.8 GHz, and 5.7–9.7 GHz, respectively. The PAs realize P1 dB of 21 dBm, Psat of 22 dBm, and PAEpeak of larger than 23%. The proposed PAs present a potential to realize multi-band transceivers without isolators.

RF Variable Gain Amplifiers (RF-VGA) are important components for integrated TV broadcast receivers. Analog and digital controlled RF-VGAs are compared in terms of linearity and an AGC loop architecture suitable for digitally controlled RF-VGA is proposed. Further linearity enhancement applicable for CMOS implementation is also discussed.

We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm2 active area.

A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.

This paper reviews and discusses a brief history of Nyquist ADCs. Bipolar flash ADCs for early development stage of HDTV and digital oscilloscopes, a Bi-CMOS two-step flash ADC using resistive interpolation for home HDTV receivers, a CMOS two-step flash ADC using capacitive interpolation for handy camcorders, pipelined ADCs using CMOS operational amplifiers, CMOS flash ADCs using dynamic comparator and digital offset compensation, SAR ADCs using low noise dynamic comparators and MOM capacitors, and hybrid ADCs are reviewed.

This paper presents two CMOS power amplifiers which realize frequency band selection. Each PA consists of two stages and uses a transformer to obtain large output power with high efficiency. Furthermore, the capacitive cross-coupling at the second stage reduces a die area of the bypass capacitance. The proposed PAs are fabricated by a 0.18 µm CMOS process. With a 3.3 V supply, the PAs achieve a output 1-dB compression point of larger than 25 dBm from 2.2 GHz to 5.4 GHz, maximum of peak power added efficiency (PAEpeak) are 30% and 27% for 2-band and 3-band PAs, respectively. The proposed PAs have advantages which are a band-selectable ability within a desired frequency range and a realization of CMOS PA with high power efficiency.

In this paper, a capacitive-cross-coupling common-gate (CCC-CG) LNA using capacitive feedback is proposed to improve the noise figure (NF). In the conventional CCC-CG LNA, the transconductance gm is determined by the input-matching condition while a lager gm is required to improve NF. gm of the proposed LNA can be increased and NF can be improved by using the added capacitive feedback. The analytical calculation shows that the proposed LNA can perform better than the conventional CCC-CG LNA. In the measurement results using a 0.18-µm CMOS technology, the gain is 10.4–13.4 dB, NF is 2.7–2.9 dB at 0.8–1.8 GHz, and IIP3 is -7 dBm at 0.8 GHz. The power consumption is 6.5 mW with a 1.8-V supply.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties for reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment.

We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

The analog IC technology, might sound old-fashioned, is still important for the future wireless systems such as 4G cellular phone systems, broadband wireless networkings, and wireless sensor networkings. The analog features and issues of the scaled CMOS transistor, the basic issue and the technology trend for the ADC as an important building block of wires systems, and the feature of the digital RF architecture proposed recently are reviewed and discussed. Higher speed and lower power consumption are expected for low SNR systems along with the further technology scaling. However, the high SNR system is not realized easily due to a decrease of signal voltage. One of the important technology trends is the digitalization of RF signal to realize the system flexibility, robustness, area shrinking, and TAT shortening.

This paper derives a maximum lock range of an injection locked ring oscillator in a direct injection method and presents an injection locked charge-pump phase-locked loop (CPPLL) with a replica of a ring oscillator. The proposed injection-locked PLL separates the injection-locked VCO from the continuous phase-tracking loop of the PLL such that can provide stable lock-state maintenance and tolerance to temperature and supply voltage variation. The measurement results show that the proposed injection-locked PLL can be tolerable to voltage variation of 11.2% in supply voltage of 1.2V. In-band noises of the injection-locked oscillator at offset frequencies of 10kHz and 100kHz are -108.2dBc/Hz and -114.6dBc/Hz, respectively.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.